As a consequence of many factors, including demand for increased portability, computing power, memory capacity and energy efficiency, electronic devices such as integrated devices, are continuously being reduced in size. The sizes of the constituent features that form the devices, e.g., electrical elements and interconnect lines, are also constantly being decreased to facilitate this size reduction.
The trend of decreasing feature size is evident, for example, in memory devices or devices such as dynamic random access memories (DRAM), Flash memory, static random access memories (SRAM), ferroelectric (FE) memories, etc. To take one example, DRAM may comprise thousands to billions of identical device components in the form of memory cells. By decreasing the sizes of the electrical device structures that comprise a memory cell and the widths and lengths of the conducting lines to access the memory cells, the memory devices can be made smaller. Additionally, storage capacities can be increased by fitting more memory cells on a given area in the memory devices.
The continual reduction in feature sizes places ever greater demands on the techniques used to form the features. For example, photolithography is commonly used to pattern features, such as conductive lines and pads. The concept of pitch can be used to describe the sizes of these features. Pitch may be defined as the distance between identical points in two neighboring features. These features are typically defined by spaces between adjacent features, which spaces are typically filled by a material, such as an insulator. As a result, pitch can be viewed as the sum of the width of a feature and of the width of the space on one side of the feature separating that feature from a neighboring feature. However, due to factors such as limitations of optics and usable light or other radiation wavelengths, photolithography techniques each have a minimum achievable pitch, below which a particular photolithographic technique cannot reliably form features. Thus, the minimum pitch of a photolithographic technique is an obstacle to continued feature size reduction.
“Pitch doubling” or “pitch multiplication” is one method for extending the capabilities of photolithographic techniques beyond their minimum pitch. One pitch multiplication method is illustrated in FIGS. 1A-1F hereof and described in U.S. Pat. No. 5,328,810, issued to Lowrey et al., the entire disclosure of which is incorporated herein by reference. With reference to FIG. 1A, a pattern of lines 10 is photolithographically formed in a photo definable layer, such as a photoresist, which overlies a layer 20 of an expendable material, which in turn overlies a substrate 30. As shown in FIG. 1B, the pattern is then transferred using an anisotropic etch to the layer 20 to form placeholders, or mandrels, 40. The photoresist lines 10 can be stripped and the mandrels 40 can be isotropically etched to increase the distance between neighboring mandrels 40, as shown in FIG. 1C. A layer 50 of spacer material is subsequently deposited over the mandrels 40, as shown in FIG. 1D. Spacers 60, i.e., the material extending or originally formed extending from sidewalls of another material, are then formed on the sides of the mandrels 40. The spacer formation is accomplished by preferentially etching the spacer material from the horizontal surfaces 70 and 80 in a directional spacer etch, as shown in FIG. 1E. The remaining mandrels 40 are then removed, leaving behind only the spacers 60, which together act as a mask for patterning, as shown in FIG. 1F. Thus, where a given pitch previously included a pattern defining one feature and one space, the same width now includes two features and two spaces, with the spaces defined by, e.g., the spacers 60. As a result, the smallest feature size possible with a photolithographic technique is effectively decreased.
While the pitch is actually halved in the example above, this reduction in pitch is conventionally referred to as pitch “doubling,” or, more generally, pitch “multiplication.” Thus, conventionally, “multiplication” of pitch by a certain factor actually involves reducing the pitch by that factor. The conventional terminology is retained herein.
Because the layer 50 of spacer material typically has a single thickness 90 (see FIGS. 1D and 1E) and because the sizes of the features formed by the spacers 60 usually correspond to that thickness 90, pitch doubling typically produces features of only one width. Devices, however, generally employ features of different sizes. For example, random access memory devices typically contain arrays of memory cells located in one, more central region of the active surface of the devices and logic devices located in the outer, so-called “peripheral” regions. In the arrays, the memory cells are connected by conductive lines and, in the periphery, the conductive lines contact landing pads for connecting arrays to logic. Peripheral features such as landing pads, however, may be larger than the conductive lines. In addition, periphery electrical devices, including peripheral transistors, may be larger than the electrical devices in the array. Moreover, even if peripheral features can be formed with the same pitch as features in the array, because mask patterns formed by pitch multiplication may be limited to those that are formed along the sidewalls of patterned photoresist, pitch multiplication by itself typically does not offer the flexibility, e.g., geometric flexibility, required to define some features, particularly when features vary in size above and below the pitch resolution of the photolithographic technique used.
To overcome such limitations, some proposed methods for forming patterns at the periphery and in the array involve separately etching patterns into the array region and then peripheral region of a substrate. A pattern in the array region is first formed and transferred to the substrate or intermediate hard mask layer using one mask and then another pattern in the periphery region is formed and separately transferred to the substrate using another mask. Because such methods require forming the pattern in the array region first before forming the other pattern in the periphery region in order to thereafter transfer the patterns to the same level to be subsequently transferred to a substrate, such methods are limited in their ability to form equivalent or higher quality patterns suitable for forming the conductive lines of the array without additional masking and etching steps required for forming the pattern for the periphery features if the array pattern is to be adequately protected. One limitation affecting the quality of the array pattern is defects. Defects may be caused, for example, by the photoresist material deposited between spacers so that features of a larger size may be formed in the periphery. Undesirably, the process conventionally used to form smaller, dimensionally critical, spacers in the pattern of the array while the other larger features in the pattern of the periphery are formed adds expense to the process flow without reducing defect potential in the array.
In addition to problems encountered in forming differently sized features on an integrated circuit device, it has been found that conventional pitch-doubling techniques may experience difficulty transferring a pattern of spacers to a substrate. In conventional methods of transferring the pattern, both the spacers and the underlying substrate layer or layers are exposed to an etchant. The etchants, however, may also etch the material of the spacers, albeit at a slower rate. Thus, over the course of subsequently forming another pattern of features in a peripheral region of the same substrate and then transferring the patterns to an underlying material, the etchant used to form the pattern of features in the peripheral region may remove an unacceptable amount of the material of the spacers before the pattern transfer is completed in both central and peripheral regions.
Also, a layer of material overlaid on the spacers while the features in the peripheral region are formed may leave residual material between adjacent spacers which may potentially cause defects or shorts therein which are subsequently transferred to one or more underlying layers. These difficulties are exacerbated by the trend towards decreasing feature size, which, for example, leads to the need to form trenches which have increasingly higher depth to width, or “aspect” ratios, increasing the potential for defects when subjected to additional steps in the process flow in order to obtain features of various sizes. Thus, in conjunction with difficulties in producing structures having different feature sizes, pattern transfer limitations make the application of pitch multiplication principles to integrated circuit device manufacture even more difficult.
Accordingly, it would be desirable to provide enhanced methods of forming features of different sizes on semiconductor device structures, especially where some features are formed below the minimum size achievable using photolithographic and other conventional lithography techniques, and in conjunction with pitch multiplication.